Dual-port memory arrays offer a higher data throughput compared to single-port memory arrays since two memory accesses may be performed simultaneously in a single clock cycle. However, dual-port memory array cells require more transistors per cell than single-port memory cells.
In order to reduce the area and cost, a dual read-port memory array has been implemented with single-read-port memory elements. Such memory arrays are more area, power, and timing efficient than a memory array implemented with dual-read-port memory elements.
FIG. 1 shows a conventional banked memory (static random access memory (SRAM)) with two read-ports and one write-port implemented with 6-transistor (6T) SRAM cells. The memory array is divided into a plurality of memory banks. In this case, two memory requests may access different banks simultaneously, but not the same memory bank.
FIG. 2 shows another conventional banked memory (SRAM) with two read-ports and one write-port implemented with 8 transistor (8T) SRAM cells. In this case, a write request may be processed separately from the read requests, but two read requests may not access the same memory bank simultaneously. The difference from the 6T case is that the write port is independent and does not cause conflicts with reads.
In a dual-read-port memory array implemented with single-read-port memory elements, certain resources within the memory array have to be shared between ports. If the two memory requests attempt to access the shared resource, a conflict occurs and the conflict is resolved by granting a shared-resource access to one of the requestors, (e.g., the first port is given priority and the second port waits or fails). This arbitration process must occur as quickly as possible so as not to negatively impact the timing performance of the storage array.